Temporary holding patch
[digispeaker-kernel.git] / arch / powerpc / boot / dts / dspeak01.dts
1 /*
2  * phyCORE-MPC5200B-tiny (pcm030) board Device Tree Source
3  *
4  * Copyright 2006 Pengutronix
5  * Sascha Hauer <s.hauer@pengutronix.de>
6  * Copyright 2007 Pengutronix
7  * Juergen Beisert <j.beisert@pengutronix.de>
8  *
9  * This program is free software; you can redistribute  it and/or modify it
10  * under  the terms of  the GNU General  Public License as published by the
11  * Free Software Foundation;  either version 2 of the  License, or (at your
12  * option) any later version.
13  */
14
15 /dts-v1/;
16
17 / {
18         model = "digispeaker,dspeak01";
19         compatible = "digispeaker,dspeak01";
20         #address-cells = <1>;
21         #size-cells = <1>;
22
23         cpus {
24                 #address-cells = <1>;
25                 #size-cells = <0>;
26
27                 PowerPC,5200@0 {
28                         device_type = "cpu";
29                         reg = <0>;
30                         d-cache-line-size = <32>;
31                         i-cache-line-size = <32>;
32                         d-cache-size = <0x4000>;        /* L1, 16K          */
33                         i-cache-size = <0x4000>;        /* L1, 16K          */
34                         timebase-frequency = <0>;       /* From Bootloader  */
35                         bus-frequency = <0>;            /* From Bootloader  */
36                         clock-frequency = <0>;          /* From Bootloader  */
37                 };
38         };
39
40         memory {
41                 device_type = "memory";
42                 reg = <0x00000000 0x04000000>;  /* 64MB */
43         };
44
45         soc5200@f0000000 {
46                 #address-cells = <1>;
47                 #size-cells = <1>;
48                 compatible = "fsl,mpc5200b-immr";
49                 ranges = <0x0 0xf0000000 0x0000c000>;
50                 bus-frequency = <0>;            /* From bootloader */
51                 system-frequency = <0>;         /* From bootloader */
52
53                 cdm@200 {
54                         compatible = "fsl,mpc5200b-cdm","fsl,mpc5200-cdm";
55                         reg = <0x200 0x38>;
56                 };
57
58                 mpc5200_pic: interrupt-controller@500 {
59                         /* 5200 interrupts are encoded into two levels; */
60                         interrupt-controller;
61                         #interrupt-cells = <3>;
62                         device_type = "interrupt-controller";
63                         compatible = "fsl,mpc5200b-pic","fsl,mpc5200-pic";
64                         reg = <0x500 0x80>;
65                 };
66
67                 timer@600 {     /* General Purpose Timer */
68                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
69                         cell-index = <0>;
70                         reg = <0x600 0x10>;
71                         interrupts = <0x1 0x9 0x0>;
72                         interrupt-parent = <&mpc5200_pic>;
73                         fsl,has-wdt;
74                 };
75
76                 timer@610 {     /* General Purpose Timer */
77                         compatible = "fsl,mpc5200b-gpt","fsl,mpc5200-gpt";
78                         cell-index = <1>;
79                         reg = <0x610 0x10>;
80                         interrupts = <0x1 0xa 0x0>;
81                         interrupt-parent = <&mpc5200_pic>;
82                 };
83
84                 gpt2: timer@620 { /* General Purpose Timer in GPIO mode */
85                         compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
86                         cell-index = <2>;
87                         reg = <0x620 0x10>;
88                         interrupts = <0x1 0xb 0x0>;
89                         interrupt-parent = <&mpc5200_pic>;
90                         gpio-controller;
91                         #gpio-cells = <2>;
92                 };
93
94                 gpt3: timer@630 { /* General Purpose Timer in GPIO mode */
95                         compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
96                         cell-index = <3>;
97                         reg = <0x630 0x10>;
98                         interrupts = <0x1 0xc 0x0>;
99                         interrupt-parent = <&mpc5200_pic>;
100                         gpio-controller;
101                         #gpio-cells = <2>;
102                 };
103
104                 gpt4: timer@640 { /* General Purpose Timer in GPIO mode */
105                         compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
106                         cell-index = <4>;
107                         reg = <0x640 0x10>;
108                         interrupts = <0x1 0xd 0x0>;
109                         interrupt-parent = <&mpc5200_pic>;
110                         gpio-controller;
111                         #gpio-cells = <2>;
112                 };
113
114                 gpt5: timer@650 { /* General Purpose Timer in GPIO mode */
115                         compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
116                         cell-index = <5>;
117                         reg = <0x650 0x10>;
118                         interrupts = <0x1 0xe 0x0>;
119                         interrupt-parent = <&mpc5200_pic>;
120                         gpio-controller;
121                         #gpio-cells = <2>;
122                 };
123
124                 gpt6: timer@660 { /* General Purpose Timer in GPIO mode */
125                         compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio";
126                         cell-index = <6>;
127                         reg = <0x660 0x10>;
128                         interrupts = <0x1 0xf 0x0>;
129                         interrupt-parent = <&mpc5200_pic>;
130                         gpio-controller;
131                         #gpio-cells = <2>;
132                 };
133
134                 rtc@800 {       // Real time clock
135                         compatible = "fsl,mpc5200b-rtc","fsl,mpc5200-rtc";
136                         device_type = "rtc";
137                         reg = <0x800 0x100>;
138                         interrupts = <0x1 0x5 0x0 0x1 0x6 0x0>;
139                         interrupt-parent = <&mpc5200_pic>;
140                 };
141
142                 gpio_simple: gpio@b00 {
143                         compatible = "fsl,mpc5200b-gpio","fsl,mpc5200-gpio";
144                         reg = <0xb00 0x40>;
145                         interrupts = <0x1 0x7 0x0>;
146                         interrupt-parent = <&mpc5200_pic>;
147                         gpio-controller;
148                         #gpio-cells = <2>;
149                 };
150
151                 gpio_wkup: gpio-wkup@c00 {
152                         compatible = "fsl,mpc5200b-gpio-wkup","fsl,mpc5200-gpio-wkup";
153                         reg = <0xc00 0x40>;
154                         interrupts = <0x1 0x8 0x0 0x0 0x3 0x0>;
155                         interrupt-parent = <&mpc5200_pic>;
156                         gpio-controller;
157                         #gpio-cells = <2>;
158                 };
159
160                 usb@1000 {
161                         compatible = "fsl,mpc5200b-ohci","fsl,mpc5200-ohci","ohci-be";
162                         reg = <0x1000 0xff>;
163                         interrupts = <0x2 0x6 0x0>;
164                         interrupt-parent = <&mpc5200_pic>;
165                 };
166
167                 dma-controller@1200 {
168                         device_type = "dma-controller";
169                         compatible = "fsl,mpc5200b-bestcomm","fsl,mpc5200-bestcomm";
170                         reg = <0x1200 0x80>;
171                         interrupts = <0x3 0x0 0x0  0x3 0x1 0x0  0x3 0x2 0x0  0x3 0x3 0x0
172                                       0x3 0x4 0x0  0x3 0x5 0x0  0x3 0x6 0x0  0x3 0x7 0x0
173                                       0x3 0x8 0x0  0x3 0x9 0x0  0x3 0xa 0x0  0x3 0xb 0x0
174                                       0x3 0xc 0x0  0x3 0xd 0x0  0x3 0xe 0x0  0x3 0xf 0x0>;
175                         interrupt-parent = <&mpc5200_pic>;
176                 };
177
178                 xlb@1f00 {
179                         compatible = "fsl,mpc5200b-xlb","fsl,mpc5200-xlb";
180                         reg = <0x1f00 0x100>;
181                 };
182
183                 i2s@2000 { /* PSC1 in i2s mode */
184                         compatible = "fsl,mpc5200b-psc-i2s","fsl,mpc5200-psc-i2s";
185                         cell-index = <0>;
186                         reg = <0x2000 0x100>;
187                         interrupts = <0x2 0x1 0x0>;
188                         interrupt-parent = <&mpc5200_pic>;
189                         codec-handle = <&pcm0>;
190                 };
191
192                 i2s@2200 { /* PSC2 in i2s mode */
193                         compatible = "fsl,mpc5200b-psc-i2s","fsl,mpc5200-psc-i2s";
194                         cell-index = <1>;
195                         reg = <0x2200 0x100>;
196                         interrupts = <0x2 0x2 0x0>;
197                         interrupt-parent = <&mpc5200_pic>;
198                 };
199
200                 serial@2400 { /* PSC3 in UART mode */
201                         device_type = "serial";
202                         compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart";
203                         port-number = <0>;
204                         cell-index = <2>;
205                         reg = <0x2400 0x100>;
206                         interrupts = <0x2 0x3 0x0>;
207                         interrupt-parent = <&mpc5200_pic>;
208                 };
209
210                 /* PSC4 is ??? */
211
212                 /* PSC5 is ??? */
213
214                 spi@2c00 { /* PSC6 in SPI mode */
215                         compatible = "fsl,mpc5200-psc-spi";
216                         cell-index = <5>;
217                         reg = <0x2c00 0x100>;
218                         interrupts = <0x2 0x4 0x0>;
219                         interrupt-parent = <&mpc5200_pic>;
220
221                         #address-cells = <1>;
222                         #size-cells = <0>;
223
224                         mmc-slot@0 {
225                                 compatible = "mmc-spi-slot";
226                                 reg = <0>;
227                                 spi-max-frequency = <50000000>;
228                                 /* Unregulated slot. */
229                                 voltage-range = <3300 3300>;
230                                 /*gpios = <&sdcsr_pio 1 0   /*  WP */
231                                 /*               &sdcsr_pio 0 1>; /* nCD */
232                         };
233                 };
234
235                 ethernet@3000 {
236                         device_type = "network";
237                         compatible = "fsl,mpc5200b-fec","fsl,mpc5200-fec";
238                         reg = <0x3000 0x400>;
239                         local-mac-address = [00 00 00 00 00 00];
240                         interrupts = <0x2 0x5 0x0>;
241                         interrupt-parent = <&mpc5200_pic>;
242                         phy-handle = <&phy0>;
243                 };
244
245                 mdio@3000 {
246                         #address-cells = <1>;
247                         #size-cells = <0>;
248                         compatible = "fsl,mpc5200b-mdio", "fsl,mpc5200-mdio";
249                         reg = <0x3000 0x400>;   /* fec range, since we need to setup fec interrupts */
250                         interrupts = <0x2 0x5 0x0>;     /* these are for "mii command finished", not link changes & co. */
251                         interrupt-parent = <&mpc5200_pic>;
252
253                         phy0:ethernet-phy@0 {
254                                 device_type = "ethernet-phy";
255                                 reg = <0x0>;
256                         };
257                 };
258
259                 ata@3a00 {
260                         device_type = "ata";
261                         compatible = "fsl,mpc5200b-ata","fsl,mpc5200-ata";
262                         reg = <0x3a00 0x100>;
263                         interrupts = <0x2 0x7 0x0>;
264                         interrupt-parent = <&mpc5200_pic>;
265                 };
266
267                 i2c@3d00 {
268                         #address-cells = <1>;
269                         #size-cells = <0>;
270                         compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
271                         cell-index = <0>;
272                         reg = <0x3d00 0x40>;
273                         interrupts = <0x2 0xf 0x0>;
274                         interrupt-parent = <&mpc5200_pic>;
275                         fsl5200-clocking;
276                         
277                         pcm0:codec@4c {
278                                 compatible = "ti,pcm1690";
279                                 reg = <0x4c>;
280                                 gpios = <
281                                         &gpt2           0 0     /* Reset */
282                                         &gpt5           0 0     /* Mute */
283                                 >;
284                         };
285                 };
286
287                 i2c@3d40 {
288                         #address-cells = <1>;
289                         #size-cells = <0>;
290                         compatible = "fsl,mpc5200b-i2c","fsl,mpc5200-i2c","fsl-i2c";
291                         cell-index = <1>;
292                         reg = <0x3d40 0x40>;
293                         interrupts = <0x2 0x10 0x0>;
294                         interrupt-parent = <&mpc5200_pic>;
295                         fsl5200-clocking;
296
297                         rtc@51 {
298                                 device_type = "rtc";
299                                 compatible = "epson,rtc8564";
300                                 reg = <0x51>;
301                         };
302                         eeprom@52 {
303                                 compatible = "atmel,24c32", "eeprom";
304                                 reg = <0x52>;
305                         };
306                 };
307
308                 sram@8000 {
309                         compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram","sram";
310                         reg = <0x8000 0x4000>;
311                 };
312
313                 ir0@670 { /* General Purpose Timer 6 in Input mode */
314                         compatible = "gpt-ir";
315                         cell-index = <7>;
316                         reg = <0x670 0x10>;
317                         interrupts = <0x1 0x10 0x0>;
318                         interrupt-parent = <&mpc5200_pic>;
319                 };
320
321                 /* This is only an example device to show the usage of gpios. It maps all available
322                  * gpios to the "gpio-provider" device.
323                  */
324                 gpio {
325                         compatible = "gpio-provider";
326
327                                                     /* mpc52xx          exp.con         patchfield */
328                         gpios = <&gpio_wkup     0 0 /* GPIO_WKUP_7      11d             jp13-3     */
329                                  &gpio_wkup     1 0 /* GPIO_WKUP_6      14c                        */
330                                  &gpio_wkup     6 0 /* PSC2_4           43c             x5-11      */
331                                  &gpio_simple   2 0 /* IRDA_1           24c             x7-6    set GPS_PORT_CONFIG[IRDA] = 0 */
332                                  &gpio_simple   3 0 /* IRDA_0                           x8-5    set GPS_PORT_CONFIG[IRDA] = 0 */
333                                  &gpt3          0 0 /* timer3           13d             x6-4       */
334                                  &gpt4          0 0 /* timer4           61c             x2-16      */
335                                  &gpt6          0 0 /* timer6           60c             x8-15      */
336                                  >;
337                 };
338         };
339
340         lpb@ff000000 {
341                 compatible = "fsl,lpb", "simple-bus";
342                 #address-cells = <2>;
343                 #size-cells = <1>;
344                 ranges = <0 0 0xff000000 0x01000000>;
345
346                 flash@0 {
347                         compatible = "cfi-flash";
348                         reg = <0 0 0x01000000>;
349                         bank-width = <2>;
350                         device-width = <2>;
351                         #size-cells = <1>;
352                         #address-cells = <1>;
353                         partition@0 {
354                                 label = "ubootl";
355                                 reg = <0x00000000 0x00040000>;
356                         };
357                         partition@40000 {
358                                 label = "kernel";
359                                 reg = <0x00040000 0x001c0000>;
360                         };
361                         partition@200000 {
362                                 label = "jffs2";
363                                 reg = <0x00200000 0x00D00000>;
364                         };
365                         partition@f00000 {
366                                 label = "uboot";
367                                 reg = <0x00f00000 0x00040000>;
368                         };
369                         partition@f40000 {
370                                 label = "oftree";
371                                 reg = <0x00f40000 0x00040000>;
372                         };
373                         partition@f80000 {
374                                 label = "space";
375                                 reg = <0x00f80000 0x00080000>;
376                         };
377                 };
378         };
379         pci@f0000d00 {
380                 #interrupt-cells = <1>;
381                 #size-cells = <2>;
382                 #address-cells = <3>;
383                 device_type = "pci";
384                 compatible = "fsl,mpc5200b-pci","fsl,mpc5200-pci";
385                 reg = <0xf0000d00 0x100>;
386                 interrupt-map-mask = <0xf800 0 0 7>;
387                 interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot
388                                  0xc000 0 0 2 &mpc5200_pic 1 1 3
389                                  0xc000 0 0 3 &mpc5200_pic 1 2 3
390                                  0xc000 0 0 4 &mpc5200_pic 1 3 3
391
392                                  0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot
393                                  0xc800 0 0 2 &mpc5200_pic 1 2 3
394                                  0xc800 0 0 3 &mpc5200_pic 1 3 3
395                                  0xc800 0 0 4 &mpc5200_pic 0 0 3>;
396                 clock-frequency = <0>; // From boot loader
397                 interrupts = <2 8 0 2 9 0 2 10 0>;
398                 bus-range = <0 0>;
399                 ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000
400                           0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
401                           0x01000000 0 0x00000000 0xb0000000 0 0x01000000>;
402         }; 
403 };